1. Field of the Invention
The present invention relates to an analog/digital converting apparatus of the successive approximation system built in, for example a microcomputer.
2. Description of the Related Art
FIG. 1 is a block diagram showing the constitution of a general analog/digital converting apparatus of the successive approximation system. A reference voltage Vref is fed into a digital/analog converter (hereinafter called as a D/A converter) 181 which divides the reference voltage Vref. A divided reference voltage 188 output from the D/A converter 181 is fed into a negative input terminal of a comparator 182. To a positive input terminal of the comparator 182 is fed an analog input voltage AVin to be converted, and a comparison result 189 of the comparator 182 is sent to a successive approximation register 183.
The data of the successive approximation register 183 is read out into a bus BS. The bus BS is connected to a control circuit 184 via a write signal line 185. A reference clock pulse 184a is applied to the control circuit 184. A control signal 186 is supplied from the control circuit 184 to the D/A converter 181, and a comparator stop signal 195a is given to the comparator 182. Between the control circuit 184 and successive approximation register 83, a signal 187 is put in and out.
FIG. 2 is a circuit diagram showing the constitution of the conventional comparator 182. A voltage input terminal X1 in which an analog input voltage AVin is fed is connected with one terminal of a sampling capacity 190. A voltage input terminal X2 to which the divided reference voltage 188 delivered from the D/A converter 181 is fed is connected to the one terminal of the sampling capacity 190 via an N-channel transistor 192. The other terminal of the sampling capacity 190 is connected to an input terminal of a CMOS inverter 193 for amplification (hereinafter called as an inverter 193), and is grounded via an N-channel transistor 195.
To the inverter 193 is converted a feedback N-channel transistor 194 in parallel to each other, and an output terminal of the inverter 193 is connected with a comparison result output terminal X3 which outputs the comparison result 189. Switch signals 191a, 192a are fed to the gates of the transistors 191, 192, while a switch signal 194a and the comparator stop signal 195a are fed to the gates of transistors 194, 195.
FIG. 3 is a block diagram showing the constitution of the conventional control circuit 184. The bus BS is connected to a start flag 102 via the write signal line 185. The comparator stop signal 195a output from the start flag 102 is fed into a frequency divider 103 and a D/A converter control circuit 101, and is output from the control circuit 184. The frequency divider 103, receiving the reference clock pulse 184a, generates switch signals 191a, 192a, 194a. The signal 187 is put in and out of the D/A converter control circuit 101 which in turn outputs a control signal 186.
The operation of this analog/digital converting operations will be explained with reference to FIG.4 showing the timing chart of each signal. When the start of operation is instructed to the start flag 102 from the bus BS through the signal line 185, the comparator stop signal 195a becomes L level as shown in FIG. 4, and the analog/digital converting apparatus starts the converting operation. As the comparator stop signal 195a first becomes L level, the transistor 195 of the comparator 182 is turned off, and the inverter 193 is prepared to compare the voltages.
In order to convert into the most significant bit, the D/A converter 181 is so controlled by the D/A converter control circuit 101 as to generate half the reference voltage Vref, that is, 1/2 Vref, and the voltage is fed to the comparator 182. On the other hand, the frequency divider 103 sequentially divides the reference clock pulse 184a as the comparator stop signal 195a becomes L level, and generates switch signals 191a, 192a, 194a shown in FIG. 4. In the comparator 182, as indicated in FIG. 4, when the switch signal 191a becomes H level, the transistor 191 is turned on, and the analog input voltage AVin is unpressed to the sampling capacity 190 to charge the sampling capacity 190 at the same time, the switch signal 194a becomes H level, and the feedback transistor 194 is turned on. As the feedback transistor 194 is turned on, a node 196 which is an input terminal of the inverter 193 is clamped at the thresh-old voltage.
Subsequently, the switch signal 194a becomes L level as is clear from FIG. 4, and the feedback transistor 194 is turned off. At this time, the node 196 is kept at the clamp potential. Moreover, the switch signal 191a is turned to L level, and the transistor 191 is turned off, with the switch signal 192a switched to H level, and the transistor 192 turned on. As a result, the reference voltage 188 is sent to the sampling capacity 190 from the D/A converter 181.
In this case, when the reference voltage 188 from the D/A converter 181 is higher than the analog input voltage AVin, the sampling capacity 190 charged by the analog input voltage AVin is further charged, and the potential of the node 196 is increased. The increase of the potential of the node 196 means that a potential higher than the threshold value of the inverter 193 is given, resulting in the comparison result 189 of L level.
When the reference voltage 188 from the D/A converter 181 is lower than the analog input voltage AVin, the sampling capacity 190 is discharged, and the potential of the node 196 is lowered. The decrease of the potential of the node 196 indicates the supply of a potential lower than the threshold value of the inverter 193, and the comparison result 189 of H level is generated.
In this way, in accordance with the potential change of the node 196, the analog input voltage AVin and reference voltage 188 from the D/A converter 181 are compared with each other. The comparison result. 189 is output after binarized in the inverter 193. The comparison result 189 is stored in tile successive approximation register 183, and the converting operation into the most significant bit is hence terminated.
At the time of the conversion into a next bit, when the analog input voltage AVin is larger than half the reference voltage, i.e., 1/2 Vref in the previous conversion result 189, a voltage obtained by adding 1/2 of half the reference voltage 1/2 Vref, that is, a fresh reference voltage, 188 of 3/4 the reference voltage Vref is output from the D/A converter 181, and is compared with the analog input voltage AVin by the comparator 182, the comparison result 189 is stored in the successive approximation register 183. In the previous conversion result 189, on the other hand, when the analog input voltage AVin is smaller than half the reference voltage Vref, a voltage attained by subtracting 1/2 of half the reference voltage 1/2 Vref, that is, a fresh reference voltage of 1/4 the reference voltage Vref is generated from the D/A converter 181, and is compared with the analog input voltage AVin in the comparator 182, the comparison result 189 is stored in the successive approximation register 183.
At the further bit conversion, when the analog input voltage AVin is larger than 3/4 of the reference voltage Vref according to the previous conversion result 189, a voltage with 1/2 of 3/4 the reference voltage Vref added, that is, a new reference voltage 188 of 7/8 the reference voltage Vref is sent out from the D/A converter 181, to be compared with the analog input voltage AVin in the comparator 182, the comparison result 189 is stored in the successive approximation register 183. When the analog input voltage AVin is smaller than 3/4 of the reference voltage Vref in the previous conversion result, a voltage obtained by subtracting 1/2 of 3/4 the reference voltage Vref, namely, a reference voltage 188 of 5/8 the reference voltage Vref is output from the D/A converter 182, where the voltage is compared with the analog input voltage AVin, and the comparison result 189 is stored in the successive approximation register 183.
In the preceding comparison result 189, when the analog input voltage AVin is larger than 1/4 of the reference voltage Vref, a voltage obtained by adding 1/2 of 1/4 the reference voltage Vref, that is, a voltage of 3/8 the reference voltage Vref is output from the D/A converter 181, and compared with the analog input voltage AVin in the comparator 182, the comparison result 189 is stored in the successive approximation register 183. In the preceding conversion result 189, meanwhile, when the analog input voltage AVin is smaller than 1/4 of the reference voltage Vref, a voltage obtained by subtracting 1/2 of 1/4 the reference voltage Vref, that is, a reference voltage 188 of 1/8 the reference voltage Vref is generated from the D/A converter 181, and is then compared with the analog input voltage AVin in the comparator 182, the comparison result is stored in the successive approximation register 183.
In this way, while the reference voltage Vref is divided and the divided voltage is sequentially increased or decreased, if the increased or decreased voltage, specifically, the reference voltage 188 is larger than the analog input voltage AVin, the reference voltage is further processed through subtracting and compared, or when the reference voltage 188 is smaller than the analog input voltage AVin, a further divided voltage is added to the reference voltage and compared, the conversion is executed sequentially from the most significant bit to the least significant bit.
This series of comparing operations is controlled by the control circuit 184.
Incidentally, the node 196 shown in FIG. 4 assumes the potential 196a when the reference voltage 188 is smaller than the analog input voltage AVin detected through comparison between the analog input voltage AVin and reference voltage 188 from the D/A converter 181 in each conversion cycle. Therefore, when the switch signal 192a becomes H level to turn on the transistor 182, the sampling capacity 190 is discharged, and the potential 196a of the node 196 is lowered from that when the switch signal 191a is H level and the transistor 191 is turned on.
As mentioned above, in the comparator of FIG. 2, the potential 196a of the node 196 starts to change, as is understood from FIG. 4, from a time point when the comparator stop signal 195a is inverted to L level. It takes a long time for the node 196 to be clamped at the threshold voltage of the inverter 193 after the feedback transistor 194 is turned on. This phenomenon is brought about because of the initialization of the inverter 193. Therefore, when the speed of the reference clock pulse 184a is increased in order to shorten the analog/digital conversion time, the voltage comparison is feared to start before the potential 196a of the node 196 reaches the threshold voltage of the inverter 193 in the conversion of the most significant bit alone, and hence the conversion accuracy is worsened.
To avoid such inconveniences as above, it may be proposed to enhance the driving ability of currents of the inverter 193 and feedback transistor 194 so as to set the potential 196a of the node 196 at the clamp potential in a short time from the initial state. However, the inverter 193 would undesirably react to the incoming noise or switching noise of the internal transistor, resulting in the deterioration of the conversion accuracy.